Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 743

Figure 15-4 describes the definition for the IEVENT register.
Offset eTSEC1:0x2_4010; eTSEC2: 0x2_5010
0 1
R BABR RXC BSY
W w1c w1c w1c
Reset
16 17
R
RXB
W w1c
Reset
Table 15-8 describes the fields of the IEVENT register.
Bits Name
0 BABR Babbling receive error. This bit indicates that a frame was received with length in excess of the MAC's
maximum frame length register while MACCFG2[Huge Frame] is set.
0 Excessive frame not received.
1 Excessive frame received.
1 RXC Receive control interrupt. A control frame was received while MACCFG1[Rx_Flow] is set. As soon as the
transmitter finishes sending the current frame, a pause operation is performed.
0 Control frame not received.
1 Control frame received.
2 BSY Busy condition interrupt. Indicates that a frame was received and discarded due to a lack of buffers.
0 No frame received and discarded.
1 Frame received and discarded.
3 EBERR Internal bus error. This bit indicates that a system bus error occurred while a DMA transaction was
underway. As a result, transferred data is expected to be partially or completely invalid.
0 No system bus error occurred.
1 System bus error occurred.
4 — Reserved
5 MSRO MIB counter overflow. This interrupt is asserted if the count for one of the MIB counters has exceeded the
size of its register.
0 MIB count not exceeding its register size.
1 MIB count exceeds its register size.
6 GTSC Graceful transmit stop complete. This interrupt is asserted for one of two reasons. Graceful stop means that
the transmitter is put into a pause state after completion of the frame currently being transmitted.
• A graceful stop, which was initiated by setting DMACTRL[GTS], is now complete.
• A transmission of a flow control PAUSE frame, which was initiated by setting TCTRL[TFC_PAUSE], is
now complete.
0 No graceful stop interrupt.
1 Graceful stop requested.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
2 3 4
EBERR MSRO
—
w1c w1c
19 20 21
MAG MMRD MMWR GRSC RXF
—
w1c w1c
Figure 15-4. IEVENT Register Definition
Table 15-8. IEVENT Field Descriptions
5 6 7 8
GTSC BABT TXC TXE TXB TXF
w1c w1c w1c
All zeros
22 23 24
w1c w1c w1c
All zeros
Description
Enhanced Three-Speed Ethernet Controllers
9 10 11 12 13
LC CRL XFUN
—
w1c w1c w1c w1c w1c
25 26 27 28 29
FGP
FIR FIQ DPE PERR
I
—
w1c w1c w1c w1c
Access: w1c
14 15
w1c
30 31
w1c
15-25