Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 547

LCLK
LAD
Address
LALE
A
TA
LA
Row lsb's
LCS n
(RAS)
LBS n
(CAS)
LGPL1
(R/W)
LBCTL
cst1
cst2
cst3
cst4
bst1
bst2
bst3
bst4
g0l0
g0l1
g0h0
g0h1
g1t1
g1t3
g2t1
g2t3
g3t1
g3t3
g4t1
g4t3
g5t1
g5t3
redo[0]
redo[1]
loop
exen
amx0
amx1
na
uta
todt
last
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Write Data Address
Row
Column lsb's
0
0
0
LALE
0
pause (due
1
1 to change
1
in AMX)
1
0
0
0
0
1
0
0
0
0
0
WSS WSS+1
Figure 10-76. Single-Beat Write Access to FPM DRAM
Write Data
Column
0 0
0 0
0 0
0 1
1 0
1 0
0 0
0 1
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 1
0 1
0 1
WSS+1 WSS+2
Enhanced Local Bus Controller
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
Bit 17
Bit 18
Bit 19
Bit 20
Bit 21
Bit 22
Bit 23
Bit 24
Bit 25
Bit 26
Bit 27
Bit 28
Bit 29
Bit 30
Bit 31
10-99