Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 746

Enhanced Three-Speed Ethernet Controllers
register are R/W and cleared upon a hardware reset. If the corresponding bits in both the IEVENT and
IMASK registers are set, the PIC receives an interrupt (for each eTSEC these are grouped into transmit,
receive, and error/diagnostic interrupts). The interrupt signal remains asserted until either the IEVENT bit
is cleared, by writing a 1 to it, or by writing a 0 to the corresponding IMASK bit.
Figure 15-5 describes the IMASK register.
Offset eTSEC1:0x2_4014; eTSEC2:0x2_5014
0
R
BREN RXCEN
W
Reset
8
R
TXCEN TXEEN
W
Reset
16
R
RXBEN
W
Reset
24
R
RXFEN
W
Reset
Table 15-9 describes the fields of the IMASK register.
Bits Name
0 BREN Babbling receiver interrupt enable
1 RXCEN Receive control interrupt enable
2 BSYEN Busy interrupt enable
3 EBERREN Ethernet controller bus error enable
4 — Reserved
5 MSROEN MIB counter overflow interrupt enable
6 GTSCEN Graceful transmit stop complete interrupt enable
7 BTEN Babbling transmitter interrupt enable
8 TXCEN Transmit control interrupt enable
9 TXEEN Transmit error interrupt enable
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-28
1 2
BSYEN EBERREN
9 10
TXBEN
17
—
25 26
— FGPIEN
Figure 15-5. IMASK Register Definition
Table 15-9. IMASK Field Descriptions
3 4
—
All zeros
11 12
TXFEN —
All zeros
19 20
MAGEN
All zeros
27 28
FIREN
All zeros
Description
Access: Read/Write
5 6
MSROEN GTSCEN
13 14
LCEN CRLEN
21 22
MMRDEN MMWREN
29 30
FIQEN DPEEN
Freescale Semiconductor
7
BTEN
15
XFUNEN
23
GRSCEN
31
PERREN