Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 602

PCI Bus Interface
13.3.2.6 PCI Error Extended Address Capture Register (PCI_EEACR)
PCI_EEACR contains fields for storing the high portion of the address associated with the first PCI error
captured. Figure 13-10
Offset 0x14
0
R
W
Reset
Figure 13-10. PCI Error Extended Address Capture Register (PCI_EEACR)
Table 13-13 describes the bit settings of the PCI_EEACR register.
Bits Name
0–31 PCI_EEA PCI error extended address. Contains the high portion of the address associated with the first
13.3.2.7 PCI Error Data Low Capture Register (PCI_EDLCR)
PCI_EDLCR contains fields for storing the data associated with the first PCI error captured.
shows the PCI_EDLCR fields.
Offset 0x18
0
R
W
Reset
Figure 13-11. PCI Error Data Low Capture Register (PCI_EDLCR)
Table 13-14 describes the bit settings of the PCI_EDLCR register.
Bits Name
0–31 PCI_EDR
13.3.2.8 PCI General Control Register (PCI_GCR)
PCI_GCR contains fields for controlling the behavior of the internal arbiter, the state of the bus signals,
and the PCI reset signal for host mode.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
13-20
shows the PCI_EEACR fields.
Table 13-13. PCI_EEACR Field Description
detected error.
Table 13-14. PCI_EDLCR Field Description
PCI error data. Contains the data associated with the first detected error.
Figure 13-12
PCI_EEA
All zeros
Description
PCI_EDR
All zeros
Description
shows the PCI_GCR fields.
Access: Read only
31
Figure 13-11
Access: Read/Write
31
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