Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 895

Important. There is a possibility that if software is severely backlogged in updating RFBPTRn, the
hardware could wrap around the ring entirely, consume exactly the remaining number of BDs and not halt
with a BSY error. If software then increments RFBPTRn to the next address (thereby equalling RBPTRn),
the hardware assumes the ring is now empty (when in fact there is only a single BD freed up). This results
in the hardware failing to maintain back pressure on the far end. Upon software incrementing RFBPTRn
a subsequent time, the wrap condition is successfully detected and hardware recognizes a nearly full ring
(rather than a nearly empty one). Since software can increment RFBPTRn by any amount, it is not possible
for hardware to determine in this case whether the user has cleared the entire ring or just one BD. Users
can eliminate the possibility of this condition occurring by ensuring that RFBPTRn is incremented by at
least two BDs each time (that is, clear at least two buffers whenever the RxBD unload routine is called).
Once the eTSEC determines that this threshold has been reached, back pressure is applied accordingly. The
type of back pressure that is applied varies according to the physical interface that is used.
• Half duplex Ethernet: No support in this mode.
• Full duplex Ethernet: An IEEE 802.3 PAUSE frame (see sect. 15.6.2.9/15-154) is issued as if the
TCTRL[TFC_PAUSE] bit was set. An internal counter tracks the time the far end controller is
expected to remain in pause (based on the setting of PTV[PT]). When that counter reaches half the
value of PTV[PT], the eTSEC reissues a pause frame if the free BD calculation for any ring is
below the threshold for that ring. For example, if PTV[PT] is set to 10 quanta, a pause frame is
re-issued when five quanta have elapsed if the free BD threshold is still not met. A practical
minimum for PTV[PT] of 4 quanta is recommended.
• FIFO packet interface: Link layer flow control is asserted through use of the RFC signal (CRS
pin). Flow control is asserted for the entire time that free BD threshold is not met. The same
mechanism is used for both GMII-style and encoded packet modes.
15.6.5.2 Software Use of Hardware-Initiated Back Pressure
15.6.5.2.1 Initialization
Software configures RBASEn and RQPRMn[LEN] according to the parameters for that ring. Then the
number of free BDs that are required to prevent the eTSEC from automatically asserting flow control are
programmed in RQPRM[FBTHR]. The receiver is then enabled.
Note: the act of programming RBASEn initializes RFBPTRn to the start of the of the ring. When the ring
is in this initial empty state, there is no concept of a last freed BD. In this case, the calculated number of
free BDs is the size of the ring. Since the BD that the hardware is currently pointing to is to be considered
in-use, the free BD count is actually one higher than the total available. As soon as the hardware consumes
a BD (by writing it back to memory), RBPTRn advances and the free BD count reflects the correct number
of available free BDs.
15.6.5.2.2 Operation
As software frees BDs from the ring, it writes the physical address of the BD just freed to RFBPTRn. The
eTSEC asserts flow control if the distance (using modulo arithmetic) between RBPTRn and RFBPTRn is
< RQPRMn[FBTHR]. In multi-ring operation, if the free BD count of any active ring drops below the
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Enhanced Three-Speed Ethernet Controllers
15-177