Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 327

7.1.5.1 Memory Management Units (MMUs)
The core MMUs support up to 4 Petabytes (2
memory (referred to as real memory in the architecture specification) for instruction and data. The MMUs
also control access privileges for these spaces on block and page granularities. Referenced and changed
status is maintained by the processor for each page to assist implementation of a demand-paged virtual
memory system. Note that software assistance is required for the device to maintain reference and changed
status. A key bit is implemented to provide information about memory protection violations prior to page
table search operations.
The LSU calculates effective addresses for data loads and stores, performs data alignment to and from
cache memory, and provides the sequencing for load and store string and multiple word instructions. The
instruction unit calculates effective addresses for instruction fetching.
After an EA is generated, its higher-order bits are translated by the appropriate MMU into physical address
bits. The lower-order EA bits are the same on the physical address which are directed to the on-chip cache
and formed the index into a four-way set-associative tag array. After translating the address, the MMU
passes the higher-order physical address bits to the cache and the cache lookup completes. For
caching-inhibited accesses or accesses that miss in the cache, the untranslated lower-order address bits are
concatenated with the translated higher-order address bits; the resulting 32-bit physical address is then
used by the memory unit and the core interface to access external memory.
The MMU also directs the address translation and enforces the protection hierarchy programmed by the
operating system in relation to the supervisor/user privilege level of the access and in relation to whether
the access is a load or store.
For instruction fetches, the IMMU looks for the address in the ITLB and in the IBAT array. If an address
hits both, the IBAT array translation is used. Data accesses cause a lookup in the DTLB and DBAT array.
In most cases, the translation is in a TLB and the physical address bits are available to the on-chip cache.
The e300 core implements four more IBAT and four more DBAT entries than the G2.
When the EA misses in the TLBs, the core provides hardware assistance for software to perform a search
of the translation tables in memory. The hardware assist consists of the following features:
• Automatic storage of the missed effective address in IMISS and DMISS
• Automatic generation of the primary and secondary hashed real addresses of the page-table entry
group (PTEG), which are readable from the HASH1 and HASH2 register locations.
The HASH data is generated from the contents of the IMISS or DMISS register. The register that
is selected depends on the miss (instruction or data) that was last acknowledged.
• Automatic generation of the first word of the page table entry (PTE) of the tables being searched
• A real page address (RPA) register that matches the format of the lower word of the PTE
• TLB access instructions (tlbli and tlbld) that are used to load an address translation into the
instruction or data TLBs
• Shadow registers for GPR0–GPR3 that allow miss code to execute without corrupting the state of
any of the existing GPRs. Shadow registers are used only for servicing a TLB miss.
See Section 7.3.5.2, "Implementation-Specific Memory Management,"
memory management for the core.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
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) of virtual memory and 4 Gigabytes (2
e300 Processor Core Overview
32
) of physical
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