Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 826

Enhanced Three-Speed Ethernet Controllers
Table 15-105 describes the fields of the GADDRn register.
Bits Name
0–31 GADDR n Represents the 32-bit value associated with the corresponding register. When RCTRL[GHTX] = 0,
GADDR0 contains entries 0–31 of the 256-entry group hash table and GADDR7 represents entries
224–255. When RCTRL[GHTX] = 1, GADDR0 contains entries 256–287 of the 512-entry extended group
hash table and GADDR7 represents entries 480–511.
15.5.3.8 DMA Attribute Registers
This section describes the two eTSEC DMA attribute registers.
15.5.3.8.1 Attribute Register (ATTR)
The attribute register defines memory access attributes and transaction types used to access buffer
descriptors, to write receive data, and to read transmit data. Snoop enable attributes may be set for reading
buffer descriptors and for reading transmit data.
Figure 15-102 describes the definition for the ATTR register.
Offset eTSEC1:0x2_4BF8; eTSEC2:0x2_5BF8;
0
R
W
Reset
Table 15-106 describes the fields of the ATTR register.
Bits Name
0–23 — Reserved
24 RDSEN Rx data snoop enable.
0 Disables snooping of all receive frames data to memory.
1 Enables snooping of all receive frames data to memory.
25 RBDSEN RxBD snoop enable.
0 Disables snooping of all receive BD memory accesses.
1 Enables snooping of all receive BD memory accesses.
26–31 — Reserved
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-108
Table 15-105. GADDR n Field Descriptions
16 17 18
—
All zeros
Figure 15-102. ATTR Register Definition
Table 15-106. ATTR Field Descriptions
Description
19 20 21 22 23 24
RDSEN RBDSEN
Description
Access: Read/Write
25 26 31
—
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