Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 504

Enhanced Local Bus Controller
LCLK
LAD
Address
LALE
A
TA
LGTA
LCS n
LBCTL
LOE
10.4.2.5 GPCM Boot Chip-Select Operation
Boot chip-select operation allows address decoding for a boot ROM before system initialization. LCS0 is
the boot chip-select output; its operation differs from other external chip-select outputs after a system reset.
When the core begins accessing memory after system reset, LCS0 is asserted for every local bus access
until BR0 or OR0 is reconfigured.
The boot chip-select also provides a programmable port size, which is configured during reset. The boot
chip-select does not provide write protection. LCS0 operates this way until the first write to OR0 and it
can be used as any other chip-select register after the preferred address range is loaded into BR0. After the
first write to OR0, the boot chip-select can be restarted only with a hardware reset.
the initial values of the boot bank in the memory controller.
Table 10-34. Boot Bank Field Values after Reset for GPCM as Boot Controller
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
10-56
Latched Address
Figure 10-43. External Termination of GPCM Access
Register Field
BR0 BA
PS
DECC
WP
MSEL
ATOM
V
Read Data
Setting
0000_0000_0000_0000_0
From RCWH[ROMLOC]
00
0
000
00
1
Table 10-34 describes
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