Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 415

9.4.1.8 DDR SDRAM Control Configuration 2 (DDR_SDRAM_CFG_2)
The DDR SDRAM control configuration register 2, shown in
configuration for the DDR controller.
Offset 0x114
0 1
R
FRC_SR — DLL_RST_DIS — DQS_CFG
W
Reset
16
R
NUM_PR
W
Reset
Figure 9-9. DDR SDRAM Control Configuration Register 2 (DDR_SDRAM_CFG_2)
Table 9-13 describes the DDR_SDRAM_CFG_2 fields.
Bits Name
0 FRC_SR
1 —
2 DLL_RST_DIS
3 —
4–5 DQS_CFG
6–8 —
9–10 ODT_CFG
11–15 —
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
2 3 4 5
19 20
Table 9-13. DDR_SDRAM_CFG_2 Field Descriptions
Force self refresh
0 DDR controller operates in normal mode.
1 DDR controller enters self-refresh mode.
Reserved. Should be cleared.
DLL reset disable. The DDR controller typically issues a DLL reset to the DRAMs when exiting self
refresh. However, this function may be disabled by setting this bit during initialization.
0 DDR controller issues a DLL reset to the DRAMs when exiting self refresh.
1 DDR controller does not issue a DLL reset to the DRAMs when exiting self refresh.
Reserved
DQS configuration
00 Only true DQS signals are used.
01 Reserved
10 Reserved
11 Reserved
Reserved
ODT configuration. This field defines how ODT is driven to the on-chip IOs. See
"DDR Control Driver Register (DDRCDR),"
(DDR2-specific, must be cleared for DDR1)
00 Never assert ODT to internal IOs
01 Assert ODT to internal IOs only during writes to DRAM
10 Assert ODT to internal IOs only during reads to DRAM
11 Always keep ODT asserted to internal IOs
Reserved.
Figure 9-9, provides more control
6 8 9
— ODT_CFG
All zeros
—
All zeros
Description
which defines the termination value that is used.
DDR Memory Controller
Access: Read/Write
10 11
—
26 27 28
D_INIT —
Section 5.4.4.12,
15
31
9-21