Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 528

Enhanced Local Bus Controller
Bits Name
8–9 G0L
10–11 G0H
12 G1T1
13 G1T3
14 G2T1
15 G2T3
16 G3T1
17 G3T3
18 G4T1/DLT3 General purpose line 4 timing 1/delay time 3. The function of this bit is determined by
19 G4T3/WAEN General purpose line 4 timing 3/wait enable. Bit function is determined by M x MR[GPL4].
20 G5T1
21 G5T3
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
10-80
Table 10-40. RAM Word Field Descriptions (continued)
General purpose line 0 lower. Defines the state of LGPL0 during the bus clock quarter phases
1 and 2 (first half phase).
00 Value defined by M x MR[G0CL]
01 Reserved
10 0
11 1
General purpose line 0 higher. Defines the state of LGPL0 during the bus clock quarter phases
3 and 4 (second half phase).
00 Value defined by M x MR[G0CL]
01 Reserved
10 0
11 1
General purpose line 1 timing 1. Defines the state (0 or 1) of LGPL1 during bus clock quarter
phases 1 and 2 (first half phase).
General purpose line 1 timing 3. Defines the state (0 or 1) of LGPL1 during bus clock quarter
phases 3 and 4 (second half phase)
General purpose line 2 timing 1. Defines state (0 or 1) of LGPL2 during bus clock quarter
phases 1 and 2 (first half phase).
General purpose line 2 timing 3. Defines the state (0 or 1) of LGPL2 during bus clock quarter
phases 3 and 4 (second half phase).
General purpose line 3 timing 1. Defines the state (0 or 1) of LGPL3 during bus clock quarter
phases 1 and 2 (first half phase).
General purpose line 3 timing 3. Defines the state (0 or 1) of LGPL3 during bus clock quarter
phases 3 and 4 (second half phase).
M x MR[GPL4].
If M x MR[GPL4] = 0 and LGPL4/LUPWAIT pin functions as an output (LGPL4), G4T1/DLT3
defines the state (0 or 1) of LGPL4 during bus clock quarter phases 1 and 2 (first half phase).
If M x MR[GPL4] = 1 and LGPL4/LUPWAIT functions as an input (LUPWAIT), if a read burst or
single read is executed, G4T1/DLT3 defines the sampling of the data bus as follows:
0 In the current word, the data bus should be sampled at the start of bus clock quarter phase
1 of the next bus clock cycle.
1 In the current word, the data bus should be sampled at the start of bus clock quarter phase
3 of the current bus clock cycle.
If M x MR[GPL4] = 0 and LGPL4/LUPWAIT pin functions as an output (LGPL4), G4T3/WAEN
defines the state (0 or 1) of LGPL4 during bus clock quarter phases 3 and 4 (second half phase).
If M x MR[GPL4] = 1 and LGPL4/LUPWAIT functions as an input (LUPWAIT), G4T3/WAEN is
used to enable the wait mechanism:
0 LUPWAIT detection is disabled.
1 LUPWAIT is enabled. If LUPWAIT is detected as being asserted, a freeze in the external
signals logical values occurs until LUPWAIT is detected as being negated.
General purpose line 5 timing 1. Defines the state (0 or 1) of LGPL5 during bus clock quarter
phases 1 and 2 (first half phase).
General purpose line 5 timing 3. Defines the state (0 or 1) of LGPL5 during bus clock quarter
phases 3 and 4 (second half phase).
Description
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