Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 308

Arbiter and Bus Monitor
6.2.4 Arbiter Interrupt Definition Register (AIDR)
Arbiter interrupt definition register (AIDR) determines the interrupt that responds to different error
conditions. Setting a bit defines the corresponding interrupt as MCP interrupt; clearing a bit defines the
corresponding interrupt as regular interrupt.
Offset 0x10
0
R
W
Reset
Table 6-5 describes AIDR fields.
Bits Name
0–25 — Write reserved, read = 0
26 ETEA Transfer error.Detection of transfer error by one of the slaves interrupt definition.
0 Detection of transfer error by one of the slaves causes regular interrupt.
1 Detection of transfer error by one of the slaves causes MCP interrupt.
27 RES Reserved transfer type. Transaction with reserved transfer type interrupt definition.
0 Transaction with reserved transfer type causes regular interrupt.
1 Transaction with reserved transfer type causes MCP interrupt.
28 ECW External control word transfer type. Transaction with external control word transfer type interrupt definition.
0 Transaction with external control word transfer type causes regular interrupt.
1 Transaction with external control word transfer type causes MCP interrupt.
29 AO Address only transfer type. Transaction with address only transfer type interrupt definition.
0 Transaction with address only transfer type causes regular interrupt.
1 Transaction with address only transfer type causes MCP interrupt.
30 DTO Data time out. Data tenure time out interrupt definition.
0 Data tenure time out causes regular interrupt.
1 Data tenure time out causes MCP interrupt.
31 ATO Address time out. Address tenure time out interrupt definition.
0 Address tenure time out causes regular interrupt.
1 Address tenure time out causes MCP interrupt.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
6-6
Figure 6-4
—
Figure 6-4. Arbiter Interrupt Definition Register (AIDR)
Table 6-5. AIDR Field Descriptions
shows the fields of AIDR.
25
All zeros
Description
Access: User read/write
26 27 28 29 30
ETEA RES ECW AO DTO ATO
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