Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 689

Bits Name
61 IFO Input FIFO overflow. The shared symmetric Input FIFO has been pushed while full.
0 No error detected
1 Input FIFO has overflowed
Note: When operated through channel-controlled access, the SEC implements flow control, and FIFO size
is not a limit to data input. When operated through host-controlled access, the AESU cannot accept
FIFO inputs larger than 256 bytes without overflowing.
62 OFU Output FIFO underflow. The shared symmetric output FIFO has been read while empty.
0 No error detected
1 Output FIFO has underflow error
63 — Reserved
14.4.3.7 AESU Interrupt Control Register (AESUICR)
The AESU interrupt control register (AESUICR), shown in
errors. For a given error (as defined in
if the corresponding bit in this register is set, then the error is ignored; no error interrupt occurs and the
interrupt status register (AESUISR) is not updated to reflect the error. If the corresponding bit is not set,
then upon detection of an error, AESUISR is updated to reflect the error, causing assertion of the error
interrupt signal, and causing the module to halt processing.
0
Field —
Reset
R/W
Addr
Table 14-30 describes the AESUICR fields.
Bits Name
0–48 — Reserved
49 ICE Integrity check error. The supplied ICV did not match the one computed by the MDEU.
0 Integrity check error enabled
1 Integrity check error disabled
50 — Reserved
51 IE Internal error. An internal processing error was detected while the AESU was processing.
0 Internal error enabled
1 Internal error disabled
52 ERE Early read error. The AESU IV register was read while the AESU was processing.
0 Early read error enabled
1 Early read error disabled
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 14-29. AESUISR Field Descriptions (continued)
Section 14.4.3.6, "AESU Interrupt Status Register
48 49 50 51 52
ICE — IE ERE CE KSE DSE ME AE OFE IFE RSV IFO OFU —
Figure 14-32. AESU Interrupt Control Register (AESUICR)
Table 14-30. AESUICR Field Descriptions
Description
Figure 14-32, controls the result of detected
53 54 55 56 57
1000
R/W
AESU 0x3_4038
Description
Security Engine (SEC) 2.2
(AESUISR)"),
58 59 60 61 62 63
14-47