Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 798

Enhanced Three-Speed Ethernet Controllers
An interrupt can be generated upon any one counter's rollover condition through a carry interrupt output
from the RMON. Each counter's rollover condition can be discretely masked from causing an interrupt by
internal masking registers. In addition, each individual counter value may be reset on read access, or all
counters may be simultaneously reset by setting ECNTRL[CLRCNT].
The majority of MIB counters are Ethernet-specific.
RMON counters do not comprehend custom VLAN tagged frames.
Affected counters include TRMGV, RMCA, RBCA, RXCF, RXPF, RXUO,
RALN, RFLR, ROVR, RJBR, TMCA, TBCA, TXPF, TXCF. Specifically,
custom VLAN tagged frames are not afforded the ability to be greater than
1518, as compared to the IEEE standard tagged frames.
15.5.3.6.1 Transmit and Receive 64-Byte Frame Counter (TR64)
Figure 15-52 describes the definition for the TR64 register.
Offset eTSEC1:0x2_4680; eTSEC2:0x2_5680
0
R
W
Reset
Figure 15-52. Transmit and Receive 64-Byte Frame Register Definition
Table 15-56 describes the fields of the TR64 register.
Bits Name
0–9 — Reserved
10–31 TR64 Transmit and receive 64-byte frame counter—Increment for each good or bad frame transmitted and received
which is 64 bytes in length, inclusive (excluding preamble and SFD but including FCS bytes).
15.5.3.6.2 Transmit and Receive 65- to 127-Byte Frame Counter (TR127)
Figure 15-53 describes the definition for the TR127 register.
Offset eTSEC1:0x2_4684; eTSEC2:0x2_5684
0
R
W
Reset
Figure 15-53. Transmit and Receive 65- to 127-Byte Frame Register Definition
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-80
9 10
—
Table 15-56. TR64 Field Descriptions
9 10
—
NOTE
TR64
All zeros
Description
TR127
All zeros
Access: Read/Write
31
Access: Read/Write
31
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