Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 709

Security Engine (SEC) 2.2
(ISR) with bits corresponding to all of these possible interrupt conditions. If an interrupt condition occurs
and the corresponding bit of the interrupt mask register (IMR) is set, the associated ISR bit is set, indicating
the presence of a pending interrupt. Whenever any bits are set in the interrupt status register, the controller
asserts its interrupt output line to the host.
To handle an interrupt, the host must read the interrupt status register to determine the source. It may then
need to do further reads of interrupt status registers of other blocks to get more detailed information about
the cause. In some cases, the host may need to take action to clear the root cause of the interrupt. After that,
the host can clear the desired bit of the interrupt status register by writing a 1 to the corresponding bit of
the interrupt clear register (ICR). If the cause of the interrupt condition has not been cleared, or if there is
some other interrupt condition from the same source, then the interrupt status register bit will clear for a
cycle and go high again, and the interrupt output line to the host remains high. If the ISR bit is successfully
cleared and no other interrupt conditions are present, the controller de-asserts its interrupt output. If any
interrupts are still pending in the interrupt status register, the interrupt output remains asserted.
Note that EU interrupt conditions may be blocked at two different levels. There is an interrupt control
register in each EU which can block particular interrupt conditions before they reach the EU's interrupt
status register, and in addition, bits of the controller's interrupt mask register (IMR) must be set to allow
interrupt conditions to reach the interrupt status register. Interrupt conditions from the channel and
controller can only be blocked through the IMR.
For typical operation it is suggested that the IMR be programmed as follows: unmask channel interrupts
while masking EU interrupts. Errors or Done signals coming from the EUs eventually cause the channel
to signal an Error or Done interrupt.
The channel can generate frequent interrupts, especially if it is configured to interrupt at the completion of
each descriptor. To make sure that the host receives the right number of interrupts, the channel Done
interrupt has a special 'queueing' feature. If multiple Channel Done interrupts are generated before the first
is cleared, then the additional interrupts are queued by the controller. When the host clears channel
interrupt, if there are no other interrupts queued from that channel, then the channel Done interrupt is
de-asserted. If other interrupts remain in the queue, the controller will de-assert the interrupt for one cycle
and then re-assert it again.
14.6.4 Controller Registers
The controller registers are described in detail in the following sections.
14.6.4.1 EU Assignment Status Register (EUASR)
The EU assignment status register (EUASR), displayed in Figure 14-41, is used to check the assignment
status of a EU to the channel.
A 1-bit field indicates to the channel whether or not the EU is assigned.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor 14-67