Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 463

Bits Name
30 EHTR Extended hold time on read accesses. Indicates with TRLX how many cycles are inserted between a read
access from the current bank and the next access.
31 EAD External address latch delay. Allow extra bus clock cycles when using external address latch (LALE).
0 No additional bus clock cycles (LALE asserted for one bus clock cycle only)
1 Extra bus clock cycles are added (LALE is asserted for the number of bus clock cycles specified by
LCRR[EADC]).
10.3.1.2.3 Option Registers (OR
Figure 10-4 shows the bit fields for ORn when the corresponding BRn[MSEL] selects the FCM machine.
Offset OR0: 0x0_5004
OR1: 0x0_500c
OR2: 0x0_5014
OR3: 0x0_501c
0
R
W
Reset
16 17 18
R
AM —
W
Reset
1
Refer to Table 10-5 for the OR0 reset value. All other option registers have all bits cleared.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
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Table 10-7. OR GPCM Field Descriptions (continued)
n
TRLX EHTR
0 0 The memory controller generates normal timing. No additional
cycles are inserted.
0 1 1 idle clock cycle is inserted.
1 0 4 idle clock cycles are inserted.
1 1 8 idle clock cycles are inserted.
)—FCM Mode
n
19 20 21 22
BCTLD — PGS CSCT CST
Figure 10-4. Option Registers (OR
Description
Meaning
AM
All zeros
23 24 25
CHT SCY
1
All zeros
) in FCM Mode
n
Enhanced Local Bus Controller
Access: Read/Write
27 28 29 30
RST TRLX EHTR
15
31
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10-15