Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 561

Chapter 12
DMA/Messaging Unit
The DMA/messaging unit supports communication between two processors on different buses, for
example, a local processor and a processor on a PCI bus. This unit operates with generic messages and
doorbell registers. Figure 12-1
This block also provides a DMA controller, which transfers blocks of data independent of the local
processor or PCI hosts. The DMA module has four high-speed DMA channels, which share buffer space
in the I/O sequencer (IOS) to facilitate the gathering and sending of data.
12.1 Features
The DMA/messaging unit includes the following features:
• Message and doorbell registers for inter-processor communication
• DMA controller
— Four DMA channels
— Concurrent execution across multiple channels with programmable bandwidth control
— Misaligned transfer capability
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
is a block diagram of the DMA/messaging unit.
DMA
DMA
DMA
DMA
Messaging Unit
Registers
DMA/Messaging Unit
Figure 12-1. DMA/Messaging Unit Block Diagram
I/O Sequencer (IOS)
12-1