Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 396

DDR Memory Controller
Figure 9-1 is a high-level block diagram of the DDR memory controller with its associated interfaces.
Section 9.5, "Functional Description,"
Request from
master
Address from
master
CSB
Data from
SDRAM
Data from
master
9.2 Features
The DDR memory controller includes these distinctive features:
• Support for DDR2 and DDR SDRAM
• 32-bit SDRAM, 16-bit SDRAM for DDR and DDR2
• Programmable settings for meeting all SDRAM timing parameters
• The following SDRAM configurations are supported:
— As many as two physical banks (chip selects), each bank independently addressable
— 64-Mbit to 4-Gbit devices depending on internal device configuration with x8/x16/x32 data
ports (no direct x4 support)
— Unbuffered and registered DRAM modules
• Open page management (dedicated entry for each logical bank)
• Automatic DRAM initialization sequence or software-controlled initialization sequence
• Automatic DRAM data initialization
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
9-2
contains detailed figures of the controller.
Row
Address
Open
Decode
Table
Figure 9-1. DDR Memory Controller Simplified Block Diagram
Address
Control
SDRAM
Control
Delay chain
FIFO
SDRAM
Control
Clock
Control
DDR SDRAM
Memory Array
MA[14:0]
MBA[2:0]
DDR SDRAM
Memory Control
MCS[0:1]
MCAS
MRAS
MWE
MDM[0:3]
MCKE
MODT[0:1]
EN
Data Qualifiers
MDQS[0:3]
Data Signals
MDQ[0:31]
EN
Clocks
MCK
MCK
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