Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 493

It is very important to ensure that the value of LBCR[BMT] is not set too low; otherwise spurious bus
time-outs may occur during normal operation—resulting in incomplete data transfers. Accordingly, the
time-out value represented by the LBCR[BMT], LBCR[BMTPS] pair must not be set below 40 bus cycles
for time-out under any circumstances.
10.4.2 General-Purpose Chip-Select Machine (GPCM)
The GPCM allows a minimal glue logic and flexible interface to SRAM, EPROM, FEPROM, ROM
devices, and external peripherals. The GPCM contains two basic configuration register groups—BR
OR .
n
Figure 10-32 shows a simple connection between an 8-bit port size SRAM device and the eLBC in GPCM
mode. Byte-write enable signals (LWE) are available for each byte written to memory. Also, the output
enable signal (LOE) is provided to minimize external glue logic. On system reset, a global (boot)
chip-select is available that provides a boot ROM chip-select (LCS0) prior to the system being fully
configured.
eLBC in GPCM
Mode
Figure 10-33 shows LCS as defined by the setup time required between the address lines and CE. The user
can configure OR [ACS] to specify LCS to meet this requirement. Generally, the attributes for the memory
n
cycle are taken from OR
fields.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
LCS n
LOE
LWE0
LA[6:25]
LAD[0:7]
Figure 10-32. Enhanced Local Bus to GPCM Device Interface
. These attributes include the CSNT, ACS, XACS, SCY, TRLX, EHTR and SETA
n
Enhanced Local Bus Controller
CE
OE
WE
Memory/Peripheral
A[19:0]
Data[7:0]
and
n
10-45