Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 176

Reset, Clocking, and Initialization
This section describes the modes configured by the reset configuration signals. Note that the reset
configuration inputs sampled values are accessible to software through memory-mapped registers
described in Section 4.5.1.3, "Reset Status Register (RSR),"
Register (SPMR)."
Implement one of the following methods to control the selection between
the reset and non-reset function of these pins.
• Resistors. Use pullup or pulldown resistors to set the desired value on
the reset configuration input signals. During the power-on and hard reset
sequences, these signals are inputs to the device.
• Active driving device. Use HRESET to control the driving device.
When HRESET is asserted, drive reset configuration values on the pins;
when HRESET is negated, stop driving the reset configuration input
signals.
4.3.1.1 Reset Configuration Word Source
The reset configuration word source options, shown in
configuration word from NOR Flash, NAND Flash, or an I
default options. The value of these signals also affects the duration of power-on and hard reset sequences.
In any case, the reset sequence does not exceed 1 ms.
CFG_RESET_SOURCE[0:3]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
4-10
NOTE
Table 4-5. Reset Configuration Words Source
Reset configuration word is loaded from NOR Flash
Reset configuration word is loaded from NAND Flash memory (8-bit small page).
Reserved
Reserved
Reset configuration word is loaded from an I
valid for any PCI frequency up to 66.666 MHz (range of 24–66.666 MHz).
Reset configuration word is loaded from NAND Flash memory (8-bit large page).
Reserved
Reserved
Hard-coded option 0. Reset configuration word is not loaded.
Hard-coded option 1. Reset configuration word is not loaded.
Hard-coded option 2. Reset configuration word is not loaded.
Hard-coded option 3. Reset configuration word is not loaded.
Hard-coded option 4. Reset configuration word is not loaded.
Reserved
Reserved
Reserved
and Section 4.5.2.1, "System PLL Mode
Table 4-5, select whether the device loads a reset
2 2
C EEPROM (I C #1) or uses hard-coded
Meaning
2
C EEPROM. PCI_CLK/PCI_SYNC_IN is
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