Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 821

15.5.3.6.46 Carry Mask Register 1 (CAM1)
While one of the below mask bits are cleared, the corresponding carry bit in CAR1 is allowed to cause
interrupt indications in register IEVENT[MSR0]. These bits all default to a set state.
describes the definition for the CAM1 register.
Offset eTSEC1:0x2_4738; eTSEC2:0x2_5738
0 1
R
M1 M1
64 127
W
Reset 1 1
16 17
R
M1 M1
RPK RFC
W
Reset 1 1
Figure 15-97. Carry Mask Register 1 (CAM1) Register Definition
Table 15-101 describes the fields of the CAM1 register.
Bits
0
1
2
3
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 15-100. CAR2 Field Descriptions (continued)
Bits Name
20 C2TMC Carry register 2 TMCA counter carry bit
21 C2TBC Carry register 2 TBCA counter carry bit
22 C2TPF Carry register 2 TXPF counter carry bit
23 C2TDF Carry register 2 TDFR counter carry bit
24 C2TED Carry register 2 TEDF counter carry bit
25 C2TSC Carry register 2 TSCL counter carry bit
26 C2TMA Carry register 2 TMCL counter carry bit
27 C2TLC Carry register 2 TLCL counter carry bit
28 C2TXC Carry register 2 TXCL counter carry bit
29 C2TNC Carry register 2 TNCL counter carry bit
30 — Reserved, should be cleared
31 C2TDP Carry register 2 TDRP counter carry bit
2 3 4 5
M1 M1 M1 M1
255 511 1K MAX
1 1 1 1
18 19 20 21
M1 M1 M1 M1
RMC RBC RXC RXP
1 1 1 1
Table 15-101. CAM1 Field Descriptions
Name
M164 Mask register 1 TR64 counter carry bit mask
M1127 Mask register 1 TR127 counter carry bit mask
M1255 Mask register 1 TR255 counter carry bit mask
M1511 Mask register 1 TR511 counter carry bit mask
Description
6 7
M1
MGV
1 0 0 0
22 23 24 25
M1 M1 M1 M1
RXU RAL RFL RCD
1 1 1 1
Description
Enhanced Three-Speed Ethernet Controllers
Figure 15-97
Access: Read/Write
13
—
0 0 0 0
26 27 28 29
M1 M1 M1 M1
RCS RUN ROV RFR
1 1 1 1
14 15
M1 M1
REJ RBY
1 1
30 31
M1 M1
RJB RDR
1 1
15-103