Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 90

Overview
1.2.2 Security Engine
A hardware encryption block is also integrated in the device. It supports many encryption algorithms
allowing for high performance data encryption and authentication as required in today's SoHo/RoBo
routers. The encryption block is compatible with the corresponding block in the MPC8280.
The security engine supports DES, 3DES, MD-5, SHA-1, AES, and RC-4 encryption algorithms in
hardware.
A block diagram of the security engine's internal architecture is shown in
module is designed to transfer 64-bit words between the internal bus and any register inside the security
engine.
An operation begins with a write of a pointer to a crypto-channel fetch register that points to a data packet
descriptor. The channel requests the descriptor and decodes the operation to be performed. The channel
then requests the controller to assign crypto execution units and fetch the keys, IVs, and data needed to
perform the given operation. The controller satisfies the requests by assigning execution units to the
channel and by making requests to the master interface. As data is processed, it is written to the individual
execution unit's output buffer and then back to system memory through the bus interface module.
Master/Slave
Interface
1.2.3 DDR Memory Controller
This fully programmable DDR SDRAM controller supports most JEDEC standard x8 or x16 DDR1 or
DDR2 memories available today, including buffered and unbuffered DIMMs. However, mixing
nonregistered and registered DIMMs in the same system is not supported. Dynamic power management
and auto-precharge modes simplify memory system design.
The DDR memory controller includes the following features:
• Support for DDR1 and DDR2 SDRAM
• 16- or 32-bit SDRAM data bus
• Programmable settings for meeting all SDRAM timing parameters
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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Crypto-
Control
Channel
Figure 1-3. Integrated Security Engine Functional Blocks
Figure 1-3. The bus interface
FIFO
FIFO
DEU MDEU
AESU
FIFO
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