Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 664

Security Engine (SEC) 2.2
14.4.1.4 DEU Reset Control Register (DEURCR)
The DEU reset control register (DEURCR), shown in
as defined by the three self-clearing bits.
0
Field
Reset
R/W
Addr
Table 14-13 describes DEURCR fields.
Bits Names
0–60 — Reserved
61 RI Reset interrupt. Writing this bit active high causes DEU interrupts signaling DONE and ERROR to be reset.
It further resets the state of the DEU interrupt status register (DEUISR).
0 Do not reset
1 Reset interrupt logic
62 MI Module initialization is nearly the same as software reset, except that the interrupt control register remains
unchanged. this module initialization includes execution of an initialization routine, completion of which is
indicated by the RESET_DONE bit in the DEU status register
0 Do not reset
1 Reset most of DEU
63 SR Software reset is functionally equivalent to hardware reset (the RESET# pin), but only for DEU. All registers
and internal state are returned to their defined reset state. Upon negation of SW_RESET, the DEU will enter
a routine to perform proper initialization of the parameter memories. The RESET_DONE bit in the DEU status
register (DEUSR) will indicate when this initialization routine is complete
0 Do not reset
1 Full DEU reset
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
14-22
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Figure 14-10. DEU Reset Control Register (DEURCR)
Table 14-13. DEURCR Field Descriptions
Figure 14-10, allows three levels reset of just DEU,
0
R/W
DEU 0x3_2018
Description
60 61 62 63
RI MI SR
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