Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 906

Enhanced Three-Speed Ethernet Controllers
The TxBD fields are detailed in
Table 15-163. Transmit Data Buffer Descriptor (TxBD) Field Descriptions
Offset Bits Name
0–1 0 R
1 PAD/CRC Padding for frames. (Valid only while it is set in the first BD and MACCFG2[PAD enable] is cleared).
2 W
3 I
4 L
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-188
Table 15-163.
Ready, written by eTSEC and user.
0 The data buffer associated with this BD is not ready for transmission. The user is free to
manipulate this BD or its associated data buffer. The eTSEC clears this bit after the buffer is
transmitted or after an error condition is encountered.
1 The data buffer, which is prepared for transmission by the user, was not transmitted or is currently
being transmitted. No fields of this BD may be written by the user once this bit is set.
If MACCFG2[PAD enable] is set, this bit is ignored.
0 Do not add padding to short frames.
1 Add PAD to frames. PAD bytes are inserted until the length of the transmitted frame equals 64
bytes. Unlike the MPC8260 which PADs up to MINFLR value, the eTSEC PADs always up to the
IEEE minimum frame length of 64 bytes. CRC is always appended to frames.
Wrap. Written by user.
0 The next buffer descriptor is found in the consecutive location.
1 The next buffer descriptor is found at the location defined in TBASE.
Interrupt. Written by user.
0 No interrupt is generated after this buffer is serviced.
1 IEVENT[TXB] or IEVENT[TXF] are set after this buffer is
interrupt if they are enabled (That is, IEVENT[TXBEN] or IEVENT[TXFEN] are set).
Last in frame. Written by user.
0 The buffer is not the last in the transmit frame.
1 The buffer is the last in the transmit frame.
Description
serviced. These bits can cause an
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