Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 49

Figure
Number
15-27 Receive Queue Filer Table Address Register Definition .................................................... 15-56
15-28 Receive Queue Filer Table Control Register Definition ..................................................... 15-56
15-29 Receive Queue Filer Table Property IDs 0, 2–15 Register Definition................................ 15-57
15-30 Receive Queue Filer Table Property ID1 Register Definition ............................................ 15-58
15-31 MRBLR Register Definition ............................................................................................... 15-61
15-32 RBDBPH Register Definition............................................................................................. 15-62
15-33 RBPTR0–RBPTR7 Register Definition .............................................................................. 15-62
15-34 RBASE Register Definition ................................................................................................ 15-63
15-35 TMR_RXTS_H/L Register Definition................................................................................ 15-64
15-36 MACCFG1 Register Definition .......................................................................................... 15-67
15-37 MACCFG2 Register Definition .......................................................................................... 15-68
15-38 IPGIFG Register Definition ................................................................................................ 15-70
15-39 Half-Duplex Register Definition......................................................................................... 15-71
15-40 Maximum Frame Length Register Definition..................................................................... 15-72
15-41 MII Management Configuration Register Definition ......................................................... 15-73
15-42 MIIMCOM Register Definition .......................................................................................... 15-73
15-43 MIIMADD Register Definition .......................................................................................... 15-74
15-44 MII Mgmt Control Register Definition............................................................................... 15-75
15-45 MIIMSTAT Register Definition .......................................................................................... 15-75
15-46 MII Mgmt Indicator Register Definition ............................................................................ 15-76
15-47 Interface Status Register Definition .................................................................................... 15-76
15-48 MAC Station Address Part 1 Register Definition ............................................................... 15-77
15-49 MAC Station Address Part 2 Register Definition ............................................................... 15-78
15-50 MAC Exact Match Address n Part 1 Register Definition ................................................... 15-78
15-51 MAC Exact Match Address x Part 2 Register Definition ................................................... 15-79
15-52 Transmit and Receive 64-Byte Frame Register Definition ................................................. 15-80
15-53 Transmit and Receive 65- to 127-Byte Frame Register Definition .................................... 15-80
15-54 Transmit and Received 128- to 255-Byte Frame Register Definition ................................ 15-81
15-55 Transmit and Received 256- to 511-Byte Frame Register Definition................................. 15-81
15-56 Transmit and Received 512- to 1023-Byte Frame Register Definition .............................. 15-82
15-57 Transmit and Received 1024- to 1518-Byte Frame Register Definition ............................ 15-82
15-58 Transmit and Received 1519- to 1522-Byte VLAN Frame Register Definition ................ 15-83
15-59 Receive Byte Counter Register Definition.......................................................................... 15-83
15-60 Receive Packet Counter Register Definition ...................................................................... 15-83
15-61 Receive FCS Error Counter Register Definition................................................................. 15-84
15-62 Receive Multicast Packet Counter Register Definition ...................................................... 15-84
15-63 Receive Broadcast Packet Counter Register Definition ..................................................... 15-85
15-64 Receive Control Frame Packet Counter Register Definition .............................................. 15-85
15-65 Receive Pause Frame Packet Counter Register Definition ................................................. 15-86
15-66 Receive Unknown OPCode Packet Counter Register Definition ....................................... 15-86
15-67 Receive Alignment Error Counter Register Definition....................................................... 15-87
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
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