Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 741

Table 15-10 describes the fields of the TSEC_ID register.
Bits Name
0–15 TSEC_ID
16–23 TSEC_REV_MJ
24–31 TSEC_REV_MN Value identifies the minor revision of the eTSEC.
15.5.3.1.2 Controller ID Register (TSEC_ID2)
The controller ID register (TSEC_ID2) is a read-only register. The TSEC_ID2 register is used to identify
the eTSEC block configuration.
Offset eTSEC1:0x2_4004; eTSEC2:0x2_5004
0
R
W
Reset 0 0 0 0 0
Table 15-6 describes the fields of the TSEC_ID2 register.
Bits Name
0–9 —
10–15 TSEC_INT
16–23 —
24–31 TSEC_CFG
Table 15-7 describes the field settings for TSEC_ID2[TSEC_INT].
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 15-5. TSEC_ID Field Descriptions
Value identifying the eTSEC (10/100/1000 Ethernet MAC).
0124 Unique identifier for eTSEC with 8 Rx and 8 Tx BD rings.
0800 Unique identifier for GMAC1 with 8 Rx and 8 Tx BD rings.
0810 Unique identifier for GMAC2 with 8 Rx and 8 Tx BD rings.
Value identifies the major revision of the eTSEC.
01 Silicon Rev 2.1
06 Silicon Rev 2.1
9 10
TSEC_INT
—
0 0 0 0 0 1 0
Figure 15-3. TSEC_ID2 Register
Table 15-6. TSEC_ID2 Field Descriptions
Reserved
Interface mode support. See
Reserved
Value identifies configuration options of the eTSEC.
00 eTSEC multiple ring, Rx TOE, Filer and Tx TOE supports are off
F0 eTSEC multiple ring, Rx TOE, Filer and Tx TOE supports are on
30 eTSEC multiple ring support is OFF and Rx TOE, Filer and Tx TOE supports are on
50 eTSEC multiple ring and filer supports are OFF and Rx TOE and Tx TOE supports are on
Table 15-7. TSEC_ID2[TSEC_INT] Field Settings
Bit
10 0 Ethernet mode not supported
1 Ethernet mode supported
11–13 Reserved
Description
15 16
0 0 0 0 0 0 0 0
Description
Table 15-7 for settings.
Mode
Enhanced Three-Speed Ethernet Controllers
Access: Read only
23 24
TSEC_CFG
—
0 0 0 0 1 1 1
31
1 0 0 0 0
15-23