Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 812

Enhanced Three-Speed Ethernet Controllers
15.5.3.6.30 Transmit Deferral Packet Counter (TDFR)
Figure 15-81 describes the definition for the TDFR register.
Offset eTSEC1:0x2_46F4; eTSEC2:0x2_56F4
0
R
W
Reset
Figure 15-81. Transmit Deferral Packet Counter Register Definition
Table 15-85 describes the fields of the TDFR register.
Bits Name
0–19 — Reserved
20–31 TDFR Transmit deferral packet counter. Increments for each frame, which was deferred on its first transmission
attempt. This count does not include frames involved in collisions.
15.5.3.6.31 Transmit Excessive Deferral Packet Counter (TEDF)
Figure 15-82 describes the definition for the TEDF register.
Offset eTSEC1:0x2_46F8; eTSEC2:0x2_56F8
0
R
W
Reset
Figure 15-82. Transmit Excessive Deferral Packet Counter Register Definition
Table 15-86 describes the fields of the TEDF register.
Bits Name
0–19 — Reserved
20–31 TEDF Transmit excessive deferral packet counter. Increments for frames aborted which were deferred for
an excessive period of time (3036 byte times).
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-94
—
All zeros
Table 15-85. TDFR Field Descriptions
Description
—
All zeros
Table 15-86. TEDF Field Descriptions
Description
Access: Read/Write
19 20
TDFR
Access: Read/Write
19 20
TEDF
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31