Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 861

Table 15-142 describes the signals shared by all interfaces.
15.6.1.6 SGMII Interface
SGMII communication using the eTSEC is accomplished through the SerDes interface. See
page 15-6 for specific signal assignments.
15.6.2 Gigabit Ethernet Controller Channel Operation
This section describes the operation of the eTSEC. First, the software initialization sequence is described.
Next, the software (Ethernet driver) interface for transmitting and receiving frames is reviewed. Frame
filtering and receive filing algorithm features are also discussed. The section concludes with interrupt
handling, inter-packet gap time, and loop back descriptions.
15.6.2.1 Initialization Sequence
This sections describes which registers are reset due to a hard or software reset and what registers the user
must initialize prior to enabling the eTSEC.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 15-141. RGMII Signals Multiplexing (continued)
eTSEC Signals
Frequency [MHz] 125
Voltage[V] 3.3/2.5
Signals No. of
I/O
(TSEC n _) Signals
RX_DV I
RX_ER I
COL I
CRS I
Sum
Table 15-142. Shared Signals
Signals I/O
MDIO I/O
MDC O
GTX_CLK125 I
Sum
RGMII Interface
Frequency [MHz] 125
Voltage[V] 2.5
Signals
(TSEC n _)
RX_CTL
1
(RX_DV/RX_ERR)
1
1
1
25
Sum
No. of Signals
1 Management interface I/O
1 Management interface clock
1 Reference clock
Enhanced Three-Speed Ethernet Controllers
No. of
I/O
Signals
I 1
12
Function
—
Table 15-1 on
15-143