Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 765

15.5.3.2.11 Transmit Timestamp Identification Register (TMR_TXTS1–2_ID)
Transmit timestamp identification register (TMR_TXTSn_ID). This register holds the identification
number of the transmitted frame corresponding to the timestamp captured in TMR_TXTSn_H/L. Each
time the eTSEC is instructed to capture the timestamp of an outgoing frame via TxFCB[PTP] the
associated field in TxFCB[PTP_ID] is stored in this register, overwriting the previous value.
This register is read only in normal operation.
TMR_TXTSn_ID register.
Offset eTSEC1:0x2_4280+4×n; eTSEC2:0x2_5280+4×n
0
R
W
Reset
Table 15-25 describes the fields of the TMR_TXTSn_ID register.
Bits Name
0–15 — Reserved
16–31 TXTS_ID Tx timestamp identification field
15.5.3.2.12 Transmit Timestamp Register (TMR_TXTS1–2_H/L)
Transmit stamp register (TMR_TXTSn_H/L). This register holds the value of the TMR_CNT_H/L when
a frame tagged for timestamp capture (via Tx FCB[PTP]) is transmitted. Upon transmission of the start of
frame symbol of such a frame, the value in TMR_CNT_H/L is copied into TMR_TXTSn_H/L.
This register is read only in normal operation.
Offset eTSEC1:0x2_42C0+8×n; eTSEC2:0x2_52C0+8×n
0
R
W
Reset
Table 15-26 describes the fields of the TMR_TXTSn_H/L register.
Bits Name
0–63 TXTS_H/L Timestamp field of the transmitted PTP packet's start of frame detection.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
—
Figure 15-20. TMR_TXTS n _ID Register Definition
Table 15-25. TMR_TXTS n _ID Register Field Descriptions
TXTS_H
Figure 15-21. TMR_TXTS n _H/L Register Definition
Table 15-26. TMR_TXTS n _H/L Register Field Descriptions
Figure 15-20 describes the definition for the
15 16
All zeros
Description
Figure 15-21 depicts TMR_TXTSn_H/L.
31 32
All zeros
Description
Enhanced Three-Speed Ethernet Controllers
Access: Read only
TXTS_ID
Access: Read only
TXTS_L
31
63
15-47