Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 996

Universal Serial Bus Interface
between system software and host controller hardware. Information concerning the initialization of the
USB module is included in the following section; however, the full details of the EHCI specification are
beyond the scope of this document.
16.6.1 Host Controller Initialization
After initial power-on or host controller reset (hardware or through USBCMD[RST]), all of the operational
registers will be at their default values. After a hardware reset, only the operational registers will be at their
default values.
The MPC8313E USB PHY and clock must be configured prior to initialization of the USB controller.
Initialization of the MPC8313E USB PHY interface is performed through software control following a
power-on reset.
In order to initialize the USB DR module, software should perform the following steps
1. Set the controller mode to host mode. Optionally set USBMODE[SDIS] (streaming disable)
Transitioning from device mode to host mode requires a host controller reset
before modifying USBMODE.
2. Optionally modify the BURSTSIZE register.
3. Program the PTS field of the PORTSC register if using a non-ULPI PHY.
4. Set CONTROL[USB_EN].
5. Write the appropriate value to the USBINTR register to enable the appropriate interrupts.
6. Write the base address of the periodic frame list to the PERIODICLIST BASE register. If there are
no work items in the periodic schedule, all elements of the periodic frame list should have their
T-Bits set.
7. Write the USBCMD register to set the desired interrupt threshold, frame list size (if applicable) and
turn the controller by setting the RS bit.
At this point, the USB DR module is up and running and the port registers begin reporting device connects.
System software can enumerate a port through the reset process (where the port is in the enabled state). At
this point, the port is active with SOFs occurring down the enabled port enabled high-speed ports, but the
schedules have not yet been enabled. The EHCI host controller will not transmit SOFs to enabled Full- or
Low-speed ports.
In order to communicate with devices via the asynchronous schedule, system software must write the
ASYNDLISTADDR register with the address of a control or bulk queue head. Software must then enable
the asynchronous schedule by writing a one to USBCMD[ASE]. In order to communicate with devices via
the periodic schedule, system software must enable the periodic schedule by writing a one to
USBCMD[PSE]. Note that the schedules can be turned on before the first port is reset (and enabled).
Any time the USBCMD register is written, system software must ensure the appropriate bits are preserved,
depending on the intended operation.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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Freescale Semiconductor