Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 252

System Configuration
The PIT consists of a 32-bit down-counter which is decremented by a clock derived from a CSB clock or
from an external 32.768-kHz crystal. The 32-bit counter decrements to zero when loaded with a initial
value from the periodic interval timer load register (PTLDR). The periodic interval timer control register
(PTCTR) is used to enable or disable the various timer functions. The periodic interval timer event register
(PTEVR) is used to report the interrupt source. The PIT function can be disabled if needed.
Figure 5-32 shows the functional PIT block diagram.
Figure 5-32. Periodic Interval Timer High Level Block Diagram
5.6.2 PIT Features
The key features of the PIT include the following:
• Maintains a 32-bit down-counter, clocked by a 32-bit prescaled input clock
• 32-bit PIT counter can be initialized by software to specific initial count value
• Provides programmable and maskable periodic interrupt
• Uses two possible clock sources: the CSB clock or an external PIT clock
• PIT function can be disabled
5.6.3 PIT Modes of Operation
The PIT unit can operate in the following modes:
• PIT enable/disable mode
• PIT periodic interrupt enable/disable mode
• PIT internal/external input clock mode
5.6.4 PIT External Signal Description
This section provides an overview and detailed descriptions of the PIT signals.
There is one distinct external input signal (PIT clock), defined in
Name Port
PIT_CLK PIT_CLK
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
5-44
PIT
Clock
System
Clock
Register Interface
Table 5-46. PIT Signal Properties
Periodic interval timer.
Periodic Periodic
Interval
Interrupt
Timer
Table
Function
5-46.
I/O Reset
I N/A
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