Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 44

Figure
Number
10-39 GPCM Relaxed Timing Write (XACS = 0, ACS = 10, SCY = 0, CSNT = 1,
TRLX = 1, CLKDIV = 4, 8) .......................................................................................... 10-53
10-40 GPCM Relaxed Timing Write (XACS = 0, ACS = 00, SCY = 1, CSNT = 1,
TRLX = 1, CLKDIV = 4, 8) .......................................................................................... 10-53
10-41 GPCM Read Followed by Read (TRLX = 0, EHTR = 0, Fastest Timing) ......................... 10-54
10-42 GPCM Read Followed by Write (TRLX = 0, EHTR = 1, One-Cycle Extended
Hold Time on Reads) ..................................................................................................... 10-55
10-43 External Termination of GPCM Access.............................................................................. 10-56
10-44 Local Bus to 8-bit FCM Device Interface........................................................................... 10-58
10-45 FCM Basic Page Read Timing (PGS = 1, CSCT = 0, CST = 0, CHT = 1,
RST = 1, SCY = 0, TRLX = 0, EHTR = 1).................................................................... 10-58
10-46 FCM Buffer RAM Memory Map for Small-Page (512-byte page) NAND
Flash Devices ................................................................................................................. 10-60
10-47 FCM Buffer RAM Memory Map for Large-Page (2-Kbyte page) NAND
Flash Devices ................................................................................................................. 10-61
10-48 FCM ECC Calculation ........................................................................................................ 10-61
10-49 ECC Placement in NAND Flash Spare Regions in Relation to FMR[ECCM] .................. 10-62
10-50 FCM Instruction Sequencer Mechanism............................................................................. 10-63
10-51 Timing of FCM Command/Address and Write Data Cycles
(for TRLX = 0, CHT = 0, CST = 1, SCY = 1, CLKDIV = 4*N)................................... 10-66
10-52 Example of FCM Command and Address Timing with Minimum Delay Parameters
(for TRLX = 0, CHT = 0, CST = 0, SCY = 0, CLKDIV = 4*N)................................... 10-67
10-53 Example of FCM Command and Address Timing with Relaxed Parameters
(for TRLX = 1, CHT = 0, CST = 1, SCY = 2, CLKDIV = 4*N)................................... 10-67
10-54 FCM Delay Prior to Sampling LFRB State ........................................................................ 10-68
10-55 FCM Read Data Timing (for TRLX = 0, RST = 0, SCY = 1, CLKDIV = 4*N) ................ 10-68
10-56 FCM Read Data Timing with Extended Hold Time (for TRLX = 0, EHTR = 1,
RST = 1, SCY = 1, CLKDIV = 4*N)............................................................................. 10-69
10-57 FCM Buffer RAM Memory Map During Boot Loading .................................................... 10-71
10-58 User-Programmable Machine Functional Block Diagram.................................................. 10-72
10-59 RAM Array Indexing .......................................................................................................... 10-73
10-60 Memory Refresh Timer Request Block Diagram ............................................................... 10-74
10-61 UPM Clock Scheme for LCRR[CLKDIV] = 2................................................................... 10-78
10-62 UPM Clock Scheme for LCRR[CLKDIV] = 4 or 8 ........................................................... 10-78
10-63 RAM Array and Signal Generation .................................................................................... 10-78
10-64 RAM Word Fields ............................................................................................................... 10-79
10-65 LCSn Signal Selection ........................................................................................................ 10-82
10-66 LBS Signal Selection .......................................................................................................... 10-83
10-67 UPM Read Access Data Sampling...................................................................................... 10-86
10-68 Effect of LUPWAIT Signal ................................................................................................. 10-87
10-69 Multiplexed Address/Data Bus for 26-Bit Addressing ....................................................... 10-88
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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Freescale Semiconductor