Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 325

7.1.2.2 Branch Processing Unit (BPU)
The BPU receives branch instructions from the fetch unit and performs CR lookahead operations on
conditional branches to resolve them early, achieving the effect of a zero-cycle branch in many cases.
The BPU uses a bit in the instruction encoding to predict the direction of the conditional branch. Therefore,
when an unresolved conditional branch instruction is encountered, the core fetches instructions from the
predicted target stream until the conditional branch is resolved.
The BPU contains an adder to compute branch target addresses and three user-control registers: the link
register (LR), the count register (CTR), and the conditional register (CR). The BPU calculates the return
pointer for sub-routine calls and saves it into the LR for certain types of branch instructions. The LR also
contains the branch target address for the Branch Conditional to Link Register (bclrx) instruction. The
CTR contains the branch target address for the Branch Conditional to Count Register (bcctrx) instruction.
The contents of the LR and CTR can be copied to or from any GPR. Because the BPU uses dedicated
registers rather than GPRs or FPRs, execution of branch instructions is largely independent from execution
of integer and floating-point instructions.
7.1.3 Independent Execution Units
The PowerPC architecture's support for independent execution units allows implementation of processors
with out-of-order instruction execution. For example, because branch instructions do not depend on GPRs
or FPRs, branches can often be resolved early, eliminating stalls caused by taken branches.
The four other execution units and the completion unit are described in the following sections.
7.1.3.1 Integer Unit (IU)
The IU executes all integer instructions. The IU executes one integer instruction at a time, performing
computations with its arithmetic logic unit (ALU), multiplier, divider, and XER register. Most integer
instructions are single-cycle instructions. The 32 GPRs hold integer operands. Stalls due to contention for
GPRs are minimized by the automatic allocation of rename registers. The core writes the contents of the
rename registers to the appropriate GPR when integer instructions are retired by the completion unit. The
e300c3 provides two integer units for greater integer instruction throughput along with enhanced
multipliers in each IU for faster multiply-instruction execution.
7.1.3.2 Floating-Point Unit (FPU)
The FPU contains a single-precision multiply-add array and the floating-point status and control register
(FPSCR). The multiply-add array allows the core to efficiently implement multiply and multiply-add
operations. The FPU is pipelined so that single- and double-precision instructions can be issued
back-to-back. The 32 FPRs are provided to support floating-point operations. Stalls due to contention for
FPRs are minimized by the automatic allocation of rename registers. The core writes the contents of the
rename registers to the appropriate FPR when floating-point instructions are retired by the completion unit.
The e300c3 core supports all floating-point data types based on the IEEE 754 standard (normalized,
denormalized, NaN, zero, and infinity) in hardware, eliminating the latency incurred by software interrupt
routines.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
e300 Processor Core Overview
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