Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 351

Vector Offset
Interrupt Type
(hex)
Program 00700
Floating-point 00800
unavailable
Decrementer 00900
Critical interrupt 00A00
Reserved 00B00–00BFF
System call 00C00
Trace 00D00
Reserved 00E00
Performance 00F00
monitor
Instruction 01000
translation miss
Data load 01100
translation miss
Data store 01200
translation miss
Instruction 01300
address
breakpoint
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 7-7. Exceptions and Interrupts (continued)
Caused by one of the following exception conditions, which correspond to bit settings in
SRR1 and arise during execution of an instruction.
Floating-point enabled exception—A floating-point enabled exception condition is
generated when the following condition is met:
(MSR[FE0] | MSR[FE1]) and FPSCR[FEX] is 1.
• FPSCR[FEX] is set by the execution of a floating-point instruction that causes an
enabled exception or by the execution of one of the Move to FPSCR instructions that
results in both an exception condition bit and its corresponding enable bit being set in
the FPSCR.
• Illegal instruction—An illegal instruction program interrupt is generated when execution
of an instruction is attempted with an illegal opcode or illegal combination of opcode and
extended opcode fields (including PowerPC instructions not implemented in the core),
or when execution of an optional instruction not provided in the core is attempted (these
do not include those optional instructions that are treated as no-ops).
• Privileged instruction—A privileged instruction program interrupt is generated when the
execution of a privileged instruction is attempted and the MSR register user privilege
bit, MSR[PR], is set. In the e300 core, this interrupt is generated for mtspr or mfspr with
an invalid SPR field if SPR[0] = 1 and MSR[PR] = 1. This may not be true for all cores
that implement the PowerPC architecture.
• Trap—A trap type program interrupt is generated when any of the conditions specified
in a trap instruction are met.
Caused by an attempt to execute a floating-point instruction (including floating-point load,
store, and move instructions) when the floating-point available bit (MSR[FP]) is cleared.
Occurs when DEC[0] changes from 0 to 1. This interrupt is enabled with MSR[EE].
Taken when cint is asserted and MSR[CE] = 1.
Occurs when a System Call (sc) instruction is executed.
Taken when MSR[SE] =1 or when the currently completing instruction is a branch and
MSR[BE] =1.
The e300 core does not generate an interrupt to this vector. Other devices may use this
vector for floating-point assist interrupts.
Caused when a configured PM counter using the pm_event_in to transition overflows.
Caused when the effective address for an instruction fetch cannot be translated by the
ITLB.
Caused when the effective address for a data load operation cannot be translated by the
DTLB.
Caused when the effective address for a data store operation cannot be translated by the
DTLB, or when a DTLB hit occurs and the change bit in the PTE must be set due to a data
store operation.
Occurs when the address (bits 0–29) in the IABR matches the next instruction to complete
in the completion unit, and IABR[30] is set. Note that the e300 core also implements
IABR2, which functions identically to IABR.
Exception Conditions
—
e300 Processor Core Overview
7-33