Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 600

PCI Bus Interface
Bits Name
26 TABT
27–31 —
13.3.2.4 PCI Error Attributes Capture Register (PCI_EATCR)
PCI_EATCR contains fields for storing information associated with the first PCI error captured.
Figure 13-8 shows the PCI_EATCR fields.
Offset 0x0C
0 1
R
— ERRTYPE
W
Reset
16
R
CMD
W
Reset
Figure 13-8. PCI Error Attributes Capture Register (PCI_EATCR)
Table 13-11 describes the bit settings of the PCI_EATCR register.
Bits Name
0 —
1–3 ERRTYPE First error type. This field is encoded to indicate the type of the first PCI error captured.
000 Address parity error
001 Write data parity error
010 Read data parity error
011 Master abort
100 Target abort
101 System error indication received
110 Parity error indication received on a read
111 Parity error indication received on a write
4–7 BN Beat number. This field provides the data beat number on which the error occurred for data parity errors.
The value of this field is undefined for other error types. The beat values are described as follows:
0000 1st beat
0001 2nd beat
0010 3rd beat
0011 4th beat
0100 5th beat
0101 6th beat
0110 7th beat
0111 8th beat
1000 9th beat or beyond (transaction larger than one cache line)
Others Reserved
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
13-18
Table 13-10. PCI_EER Field Descriptions (continued)
Target abort. Generate an interrupt when the corresponding bit of the PCI_ESR is 1.
Reserved
3 4
BN
19 20
—
Table 13-11. PCI_EATCR Field Descriptions
Description
7 8 9 10
— TS
All zeros
23 24
BE
All zeros
Description
Reserved
Access: Read/Write
11 12
ES
27 28 29 30
— PB
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