Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 943

Bits Name
31–16 — Reserved, should be cleared.
15 AS Asynchronous schedule status. Reports the current real status of the asynchronous schedule. The
USB DR controller is not required to immediately disable or enable the asynchronous schedule when
software transitions USBCMD[ASE]. When this bit and USBCMD[ASE] have the same value, the
asynchronous schedule is either enabled (1) or disabled (0). Only used in host mode.
0 Disabled
1 Enabled
14 PS Periodic schedule status. Reports the current real status of the periodic schedule. The USB DR
controller is not required to immediately disable or enable the periodic schedule when software
transitions USBCMD[PSE]. When this bit and USBCMD[PSE] have the same value, the periodic
schedule
is either enabled (1) or disabled (0). Only used in host mode.
0 Disabled
1 Enabled
13 RCL Reclamation. Used to detect an empty asynchronous schedule. Only used by the host mode.
0 Non-empty asynchronous schedule
1 Empty asynchronous schedule
12 HCH HC haIted. This bit is a zero whenever USBCMD[RS] is a one. The USB DR controller sets this bit to
one after it has stopped executing because of USBCMD[RS] being cleared, either by software or by
the host controller hardware (for example, internal error). Only used in host mode.
0 Running
1 Halted
11 — Reserved, should be cleared.
10 ULPII ULPI interrupt. An event completion to the viewport register sets this bit. If the ULPI enables the
USBINTR[ULPIE] to be set, the USB interrupt (UI) will occur.
9 — Reserved, should be cleared.
8 SLI DCSuspend. This is a non-EHCI bit. When a device controller enters a suspend state from an active
state, this bit is set. The device controller clears the bit upon exiting from a suspend state. Only used
by the device controller.
0 Active
1 Suspended
7 SRI Host mode:
• This is a non-EHCI status bit. In host mode, this bit will be set every 125 us, provided the PHY clock
Device mode:
• SOF received. When the USB DR controller detects a Start Of (Micro)Frame, this bit will be set.
Software writes a 1 to this bit to clear it.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 16-11. USBSTS Register Field Descriptions
is present and running (for example, the port is NOT suspended), and can be used by the host
controller driver as a time base.
When a SOF is extremely late, the DR controller will automatically set this bit to indicate that an
SOF was expected. Therefore, this bit will be set roughly every 1 msec in device FS mode and
every 125 msec in HS mode and will be synchronized to the actual SOF that is received. Because
the controller is initialized to FS before connect, this bit will be set at an interval of 1 msec during
the prelude to the connect and chirp.
Description
Universal Serial Bus Interface
16-15