Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 634

PCI Bus Interface
PCI_CLK
PCI_FRAME
PCI_IRDY
PCI_DEVSEL
PCI_TRDY
PCI_STOP
PCI_CLK
PCI_FRAME
PCI_IRDY
PCI_DEVSEL
PCI_TRDY
PCI_STOP
Note that when an initiator is terminated by PCI_STOP, it must negate its REQn signal for a minimum of
two PCI clocks (of which one clock is needed for the bus to return to the idle state). If the initiator intends
to complete the transaction, it should reassert its REQn immediately following the two clocks or potential
starvation may occur. If the initiator does not intend to complete the transaction, it can assert REQn
whenever it needs to use the PCI bus again.
The PCI controller terminates a transaction in the following cases:
• Eight PCI clock cycles have elapsed between data phases. This is a 'latency disconnect' (see
Figure 13-50).
• AD[1:0] is 0bx1 (a reserved burst ordering encoding) during the address phase and one data phase
has completed.
• The PCI command is a configuration command and one data phase has completed.
• A streaming transaction crosses a 4-Kbyte page boundary.
• A streaming transaction runs out of I/O sequencer buffer entries.
• A cache line wrap transaction has completed a cache line transfer.
Another target-initiated termination is the retry termination. Retry refers to termination requested because
the target is currently in a state where it is unable to process the transaction. This can occur because no
buffer entries are available in the I/O sequencer, or the sixteen clock latency timer has expired without
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
13-52
Disconnect A
Latency disconnect
Figure 13-52. Target-Initiated Terminations
Disconnect B
PCI_CLK
PCI_FRAME
PCI_IRDY
PCI_DEVSEL
PCI_TRDY
PCI_STOP
Target abort
Retry
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