Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 556

Sequencer
Table 11-3 describes POBARn fields.
Bits Name
0–11 — Reserved
12–31 BA Base address. This field contains the starting address of the outbound translated window. This field
corresponds to the most-significant 20 bits of a 32-bit address.
11.4.3 PCI Outbound Comparison Mask Registers (POCMR n )
The PCI outbound comparison mask register (POCMRn) defines the size and destination of the outbound
translation window. It also defines some properties of the window in the PCI address space. See
Section 11.5.1, "Transaction Forwarding,"
fields.
Offset 0x10, 0x28, 0x40
0x58, 0x70, 0x88
0 1 2
R
EN IO
W
Reset
Figure 11-4. PCI Outbound Comparison Mask Registers (POCMR n )
Table 11-4 describes the bit settings of the POCMRn register.
Bits Name
0 EN Enable. Enables the address translation window.
0 Address translation is disabled for this window.
1 Address translation is enabled for this window. Local addresses that match the definition of the window will
be recognized by the device and translated to the PCI memory space.
1 IO I/O space. Determines whether the window is mapped to the PCI memory space or PCI I/O space.
0 Memory space
1 I/O space
2–11 — Reserved, should be cleared.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
11-4
Table 11-3. POBAR n Field Descriptions
for more information.
11 12
—
Table 11-4. POCMR n Field Descriptions
Description
Figure 11-4
All zeros
Description
shows the POCMRn register
Access: Read/Write
CM
Freescale Semiconductor
31