Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 697

14.5.1 Channel Registers
14.5.1.1 Crypto-Channel Configuration Register (CCCR)
The crypto-channel configuration register (CCCR) contains five operational bits permitting configuration
of the channel as shown in
0
Field
Reset
R/W
Addr
32
Field
Reset
R/W
Addr
Bits Names
0–29 — Reserved, set to zero
30 CON Continue bit
0 No special action.
1 Causes the same channel reset actions as bit R, except that the fetch FIFO and the lower half of the CCR
register are not cleared. After the reset sequence is complete, this bit automatically returns to 0 and the
channel resumes normal operation, servicing the next descriptor pointer in the fetch FIFO, if any.
31 R Reset channel
0 No special action.
1 Causes a software reset of the channel, clearing all its internal state. The details of the software reset
actions depend upon what the channel is doing when the bit is set:
• If the R bit is set while the channel is requesting an EU assignment from the controller, the channel
cancels its request by asserting the release output signals. The channel then resets all its registers,
clears the R bit, and return the channel state machine to the idle state.
• If the R bit is set after the channel has been assigned an EU, the channel requests a write from the
controller to set the software reset bit of the EU. If a secondary EU has been reserved, the channel
requests a write to reset that EU as well. The channel next asserts the appropriate release signal to
notify the controller that the channel has finished with the reserved EU(s). The channel then resets all
the registers, clears the RESET bit and returns the channel state machine to the idle state.
32–54 — Reserved, set to zero
55 BS Burst size—The SEC accesses long text-data parcels in main memory through bursts of programmable size:
0 Burst size is 64 bytes
1 Burst size is 128 bytes
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Figure 14-36. Table 14-31
—
Figure 14-36. Crypto-Channel Configuration Register (CCCR)
Table 14-31. CCCR Field Descriptions
describes the CCR.
—
0
R/W
Channel_1 0x3_1108
54 55 56 57
BS IWSE AWSE EAE CDWE
0
R/W
Channel_1 0x3_110C
Description
Security Engine (SEC) 2.2
29
58 59 60 61
— NT
30 31
CON R
62 63
CDIE —
14-55