Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 421

9.4.1.13 DDR SDRAM Data Initialization (DDR_DATA_INIT)
The DDR SDRAM data initialization register, shown in
initialize memory if DDR_SDRAM_CFG2[D_INIT] is set.
Offset 0x128
0
R
W
Reset
Figure 9-14. DDR SDRAM Data Initialization Configuration Register (DDR_DATA_INIT)
Table 9-19 describes the DDR_DATA_INIT fields.
Bits Name
0–31 INIT_VALUE Initialization value. Represents the value that DRAM is initialized with if DDR_SDRAM_CFG2[D_INIT]
is set.
9.4.1.14 DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
The DDR SDRAM clock control configuration register, shown in
adjustment.
Offset 0x130
0 4
R
— CLK_ADJUST
W
Reset 0 0 0 0 0
Figure 9-15. DDR SDRAM Clock Control Configuration Register (DDR_SDRAM_CLK_CNTL)
Table 9-20 describes the DDR_SDRAM_CLK_CNTL fields.
Bits Name
0–4 — Reserved
5–7 CLK_ADJUST Clock adjust.
000
001
010
011
100
101–111 Reserved
8 — Reserved, should be cleared.
9–31 — Reserved
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 9-19. DDR_DATA_INIT Field Descriptions
5 7 8
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 9-20. DDR_SDRAM_CLK_CNTL Field Descriptions
Clock is launched aligned with address/command
Clock is launched 1/4 applied cycle after address/command
Clock is launched 1/2 applied cycle after address/command
Clock is launched 3/4 applied cycle after address/command
Clock is launched 1 applied cycle after address/command
Figure 9-14, provides the value that is used to
INIT_VALUE
All zeros
Description
Figure
—
Description
DDR Memory Controller
Access: Read/Write
9-15, provides a 1/4-cycle clock
Access: Read/Write
31
31
0
9-27