Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 204

Reset, Clocking, and Initialization
Address 0x0_0A00
0 1
R LBCM DDRCM
W
1
Reset n n
16
R
W
Reset n n
1
See Table 4-34 for reset values.
Table 4-34 defines the system PLL mode register bit fields.
Bits Name
0 LBCM Local bus memory controller clock mode.
1 DDRCM DDR SDRAM memory controller clock mode.
2–3 — Reserved, should be cleared.
4–7 SPMF System PLL multiplication factor
8 CKID SYS_CLK_IN division factor. Reflects the value of
CFG_CLKIN_DIV input signal during the reset flow.
9–15 COREPLL Core PLL configuration.
16–31 — Reserved, should be cleared.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
4-38
2 3 4
SPMF
—
n n n n
n n n n
Figure 4-13. System PLL Mode Register
Table 4-34. System PLL Mode Register Bit Settings
Meaning
7 8 9
CKID
n n n n
—
n n n n
Section 4.3.2.1, "Reset Configuration Word Low
Register (RCWLR)"
Section 4.3.2.1, "Reset Configuration Word Low
Register (RCWLR)"
Section 4.3.2.1.1, "System PLL Configuration"
Section 4.3.1.2, "SYS_CLK_IN Division"
See the hardware specifications for this device
—
Access: Read only
COREPLL
n n n n
n n n n
Description
—
Freescale Semiconductor
15
n n
31
n n