Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 517

The timing parameters are summarized in
Option Register
TRLX
0
0
1
1
1
In the parameters, SCY refers to a delay of OR n [SCY] clock cycles.
10.4.3.3.5 FCM Extended Read Hold Timing
Allowance for slow output driver turn-off when reading NAND Flash EEPROMs is made via setting of
ORn[EHTR] and ORn[TRLX]. The extended read data hold time, shown at t
Figure 10-56, is a delay inserted by FCM between the last data read and another eLBC memory access
(requiring LALE assertion). LCSn is negated during t
time to disable their drivers.
LCLK
(unused)
LALE
(unused)
LCS n
LFCLE/
LFALE
LFRE
LAD[0:7]
TA
Figure 10-56. FCM Read Data Timing with Extended Hold Time
10.4.3.4 FCM Boot Chip-Select Operation
Boot chip-select operation allows address decoding for a boot ROM before system initialization. LCS0 is
the boot chip-select output; its operation differs from other external chip-select outputs after a system reset.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table
Table 10-37. FCM Read Data Timing Parameters
Timing Parameter (LCLK Clock Cycles)
Attributes
RST t
RP
0 ¾+SCY
1 1+SCY
0 ½+2×SCY
1 1+2×SCY
read cycle
Notes: t = Read data cycle time.
RC
t
EHTR
(for TRLX = 0, EHTR = 1, RST = 1, SCY = 1, CLKDIV = 4*N)
10-37.
t t
RHT WS
1 SCY 2+SCY
1 SCY 2+SCY
2 2×SCY 3+2×SCY 8×(2+SCY)
2 2×SCY 3+2×SCY 8×(2+SCY)
to allow external devices and bus transceivers
EHTR
t
EHTR
t
RC
last read data
= Extended read data hold time.
Enhanced Local Bus Controller
1
t t
RC WRT
4×(2+SCY)
4×(2+SCY)
in Figure 10-45
EHTR
and
10-69