Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 631

13.4.3.6 Bus Transactions
The timing diagrams in this section show the relationship of significant signals involved in bus
transactions.
Note the following conventions:
• When a signal is drawn as a solid line, it is actively being driven by the current initiator or target.
• When a signal is drawn as a dashed line, no agent is actively driving it.
• Three-stated signals with slashes between the two rails have indeterminate values.
• The terms 'edge' and 'clock edge' refer to the rising edge of the clock.
• The terms 'asserted' and 'negated' refer to the globally visible state of the signal on the clock edge,
and not to signal transitions.
• The symbol
13.4.3.7 Read and Write Transactions
Both read and write transactions begin with an address phase followed by a data phase. The address phase
occurs when PCI_FRAME is asserted for the first time, and the AD[31:0] signals contain a byte address
and the PCI_C/BE[3:0] signals contain a bus command. The data phase consists of the actual data transfer
and possible wait cycles; the byte enable signals remain actively driven from the first clock of the data
phase through the end of the data transfer.
A read transaction starts when PCI_FRAME is asserted for the first time and the PCI_C/BE[3:0] signals
indicate a read command.
PCI_CLK
PCI_AD[31:0]
PCI_C/BE[3:0]
PCI_FRAME
PCI_IRDY
PCI_DEVSEL
PCI_TRDY
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
represents a turnaround-cycle.
Figure 13-48 shows an example of a single beat read transaction.
ADDR
CMD
Figure 13-48. Single Beat Read Example
BYTE ENABLES
PCI Bus Interface
DATA
13-49