Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 897

• Recognition of incoming PTP packet through filer rule match
• Phase aligned adjustable (divide by N) clock output
• Supports all Ethernet modes supported by the eTSEC, including full- and half-duplex modes
• Supports both master and slave modes
• Supports timestamp of nano-second resolution
15.6.6.2 Timer Logic Overview
The 1588 timer module can be partitioned into four different sub-modules as shown in
1588 Timer
Clock
TMRCK
15.6.6.3 Timestamp Insertion on the Received Packets
Every incoming packet's 8-byte timestamp is inserted into the packet data buffer as padding alignment
bytes. Timestamp insertion into the data buffer requires RCTRL[PAL] to be set to a value greater than or
equal to 8 and the control bit RCTRL[TS] bit to be set.
15.6.6.3.1 Timestamp Point
The required timestamp point, as specified in the IEEE 1588 Specification Sep-2004 (IEC 61588 First
Edition), is shown in Figure 15-140. From this, it is clear that the end of the SFD is the critical point in the
MII data stream.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Timestamp
Register Array
TMRREG
SFD Detection
Rx & Tx
TMRMAC
Figure 15-139. 1588 Timer Design Partition
Enhanced Three-Speed Ethernet Controllers
Figure
eTSEC
SEL
Ethernet MAC
Rx Pins Tx Pins
15-139.
15-179