Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 427

be constructed using x8, x16, or x32 memory devices. The memory technologies supported are 64 Mbits,
128 Mbits, 256 Mbits, 512 Mbits, 1 Gbit, 2 Gbits, and 4 Gbits. Four data qualifier (DQM) signals provide
byte selection for memory accesses.
An 8-bit DDR SDRAM device has a DQM signal and eight data signals
(DQ[0:7]). A 16-bit DDR SDRAM device has two DQM signals associated
with specific halves of the 16 data signals (DQ[0:7] and DQ[8:15]).
Table 9-24 shows the DDR memory controller's relationships between data byte lane0–3, MDM[0:3],
MDQS[0:3], and MDQ[0:31] when DDR SDRAM memories are used with x8 or x16 devices.
Data Byte Lane
0 (MSB)
9.5.1.1 Supported DDR SDRAM Organizations
Although the DDR memory controller multiplexes row and column address bits onto 15 memory address
signals and 3 logical bank select signals, a physical bank may be implemented with memory devices
requiring fewer than 30 address bits. The physical bank may be configured to provide from 12 to 15 row
address bits, plus 2 or 3 logical bank-select bits and from 8–11 column address bits.
Table 9-25 and Table 9-26
controller.
DDR SDRAM is limited to 29 total address bits.
SDRAM Device Device Configuration
64 Mbits
1
64 Mbits
128 Mbits
128 Mbits
256 Mbits
256 Mbits
512 Mbits
512 Mbits
1 Gbits
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 9-24. Byte Lane to Data Relationship
Data Bus Mask
MDM[0]
1 MDM[1]
2 MDM[2]
3 MDM[3]
describe DDR SDRAM device configurations supported by the DDR memory
Table 9-25. Supported DDR1 SDRAM Device Configurations
Row x Column x
Sub-bank Bits
8 Mbits x 8
4 Mbits x 16
16 Mbits x 8
8 Mbits x 16
32 Mbits x 8
16 Mbits x 16
64 Mbits x 8
32 Mbits x 16
128 Mbits x 8
NOTE
Data Bus Strobe
MDQS[0]
MDQS[1]
MDQS[2]
MDQS[3]
NOTE
32-Bit Bank Size
12 x 9 x 2 32 Mbytes
12 x 8 x 2 16 Mbytes
12 x 10 x 2 64 Mbytes
12 x 9 x 2 32 Mbytes
13 x 10 x 2 128 Mbytes
13 x 9 x 2 64 Mbytes
13 x 11 x 2 256 Mbytes
13 x 10 x 2 128 Mbytes
14 x 11 x 2 512 Mbytes
DDR Memory Controller
Data Bus
MDQ[0:7]
MDQ[8:15]
MDQ[16:23]
MDQ[24:31]
Two Banks of Memory
64 Mbytes
32 Mbytes
128 Mbytes
64 Mbytes
256 Mbytes
128 Mbytes
512 Mbytes
256 Mbytes
1 Gbyte
9-33