Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 937

16.3.1.3 Host Controller Structural Parameters (HCSPARAMS)
HCSPARAMS contains structural parameters such as the number of downstream ports.
the HCSPARAMS register.
Offset 0x2_3104
31 28 27
R
—
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 16-4. Host Controller Structural Parameters (HCSPARAMS)
Table 16-6 provides bit descriptions for the HCSPARAMS register.
Bits Name
31–28 — Reserved, should be cleared.
27–24 N_TT Number of transaction translators. This is a non-EHCI field. This field indicates the number of embedded
transaction translators associated the module. The reset value of this field is always 1 after the USBDR
controller is configured as a host by writing 0x3 to USBMODE; else, the reset value is always 0. See
Section 16.9.1, "Embedded Transaction Translator Function."
23–20 N_PTT Ports per transaction translator. This is a non-EHCI field. The number of ports assigned to each
transaction translator. This is equal to N_PORTS.
19–17 — Reserved, should be cleared.
16 PI Port indicators. Indicates whether the ports support port indicator control. The reset value of this field
is always 0 after the USBDR controller is configured as a host by writing 0x3 to USBMODE; else, the
reset value is always 1.
1 The port status and control registers include a R/W field for controlling the state of the port indicator.
15–12 N_CC Number of companion controllers associated with the DR controller. Always 0.
11–8 N_PCC Number ports per CC. This field indicates the number of ports supported per internal companion
controller. Always 0.
7–5 — Reserved, should be cleared.
4 PPC Power port control. Indicates whether the host controller supports port power control.The reset value of
this field is always 0 after the USBDR controller is configured as a host by writing 0x3 to USBMODE;
else, the reset value is always 1.
1 Ports have power port switches.
3–0 N_PORTS Number of ports. Number of physical downstream ports implemented for host applications. The value
of this field determines how many port registers are addressable in the operational register. The reset
value of this field is always 0 after the USBDR controller is configured as a host by writing 0x3 to
USBMODE; else, the reset value is always 1.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
24 23 20 19
N_TT N_PTT
Table 16-6. HCSPARAMS Register Field Descriptions
17 16 15 12 11
PI N_CC
—
1 0 0 0 0 0 0 0 0 0 0 0
Description
Universal Serial Bus Interface
Figure 16-4
Access: Read-only
8 7 5 4
N_PCC PPC
—
1
shows
3 0
N_PORTS
0 0 0 1
16-9