Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 369

Interrupt ID Number
81–83
84
85
86–89
90
91
92–127
8.5.3 System Internal Interrupt Pending Registers (SIPNR_H and
SIPNR_L)
Each bit in SIPNR_H and SIPNR_L, shown in
interrupt source. (Implemented bits are listed in
interrupt controller sets the corresponding SIPNR bit. When a pending interrupt is handled, the user clears
the SIPNR bit by clearing the corresponding event register bit.
Note that SIPNR bit positions are not changed according to relative priority.
Offset 0x08
0
R
W
Reset
Figure 8-4. System Internal Interrupt Pending Register (SIPNR_H)
Table 8-7 lists implemented SIPNR_H fields. Note that these field descriptions are also valid for SIFCR_H
and SIMSR_H.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 8-6. IVEC/CVEC/MVEC Field Definition (continued)
Interrupt Meaning
Reserved
GTM3
GTM7
Reserved
GTM1
GTM5
Reserved
n (Implemented bits are listed in
INT
Table 8-7. SIPNR_H/SIFCR_H/SIMSR_H Bit Assignments
Bits
0
1
2
3
4
5
6
7–23
24
25
Integrated Programmable Interrupt Controller (IPIC)
Figure 8-4 and Figure
Table 8-7.) When an interrupt request is received, the
Table
All zeros
Field
TSEC1 Tx
TSEC1 Rx
TSEC1 Err
TSEC2 Tx
TSEC2 Rx
TSEC2 Err
USB DR
—
UART1
UART2
Interrupt Vector
0b101_0001–0b101_0011
0b101_0100
0b101_0101
0b101_0110–0b101_1001
0b101_1010
0b101_1011
0b101_1100–0b111_1111
8-5, may be assigned an internal
Access: Read only
8-7.)
31
8-11