Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 818

Enhanced Three-Speed Ethernet Controllers
15.5.3.6.42 Transmit Undersize Frame Counter (TUND)
Figure 15-93 describes the definition for the TUND register.
Offset eTSEC1:0x2_4728; eTSEC2:0x2_5728
0
R
W
Reset
Figure 15-93. Transmit Undersize Frame Counter Register Definition
Table 15-97 describes the fields of the TUND register.
Bits Name
0–19 — Reserved
20–31 TUND Transmit undersize frame counter. Increments for every frame less then 64 bytes, with a correct FCS value.
15.5.3.6.43 Transmit Fragment Counter (TFRG)
Figure 15-94 describes the definition for the TFRG register.
Offset eTSEC1:0x2_472C; eTSEC2:0x2_572C
0
R
W
Reset
Table 15-98 describes the fields of the TFRG register.
Bits Name
0–19 — Reserved
20–31 TFRG Transmit fragment counter. Increments for every frame less then 64 bytes, with an incorrect FCS value.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-100
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Table 15-97. TUND Field Descriptions
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Figure 15-94. Transmit Fragment Counter Register Definition
Table 15-98. TFRG Field Descriptions
19 20
All zeros
Description
19 20
All zeros
Description
Access: Read/Write
31
TUND
Access: Read/Write
31
TFRG
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