Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 790

Enhanced Three-Speed Ethernet Controllers
Bits Name
14 No BackOff
15 Excess Defer
16–19 Retransmission
Maximum
20–25 —
26–31 Collision Window This is a programmable field representing the slot time or collision window during which collisions
15.5.3.5.5 Maximum Frame Length Register (MAXFRM)
The MAXFRM register is written by the user.
Offset eTSEC1:0x2_4510; eTSEC2:0x2_5510
0
R
W
Reset 0 0 0 0 0
Table 15-44 describes the fields of the MAXFRM register.
Bits Name
0–15 —
16–31 Maximum Frame By default this field is set to 0x0600 (1536 bytes). It sets the maximum Ethernet frame size in both
15.5.3.5.6 MII Management Configuration Register (MIIMCFG)
The MIIMCFG register is written by the user to configure all MII management operations. Note that MII
management hardware is shared by all eTSECs. Thus, only through the MIIM registers of eTSEC1 can
external PHYs be accessed and configured. Note: when an eTSEC is configured to use RTBI,
configuration of the RTBI (described in
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-72
Table 15-43. HAFDUP Field Descriptions (continued)
No backoff. This bit is cleared by default.
0 The Tx MAC follows the binary exponential back off rule.
1 The Tx MAC immediately re-transmits following a collision.
Excessively deferred. This bit is set by default.
0 The Tx MAC aborts the transmission of a packet that is excessively deferred.
1 The Tx MAC allows the transmission of a packet that is excessively deferred.
This is a programmable field specifying the number of retransmission attempts following a collision
before aborting the packet due to excessive collisions. The standard specifies the attempt limit to
be 0xF (15d). Its default value is 0xF.
Reserved
occur in properly configured networks. Because the collision window starts at the beginning of
transmission, the preamble and SFD are included. Its default of 0x37 (55d) corresponds to the
count of frame bytes at the end of the window.
—
0 0 0 0 0 0 0
Figure 15-40. Maximum Frame Length Register Definition
Table 15-44. MAXFRM Descriptions
Reserved
the transmit and receive directions. (Refer to MACCFG2[Huge Frame].)
Note that if MACCFG2[Huge Frame] = 0, the value of this field must be less than or equal to
MRBLR[MRBL] × (minimum number of RxBDs per ring). See
Configuration 2 Register (MACCFG2),"
Register (MRBLR)," and Section 15.6.7.3, "Receive Buffer Descriptors
Section 15.5.4, "Ten-Bit Interface
Description
Figure 15-40 shows the MAXFRM register.
15 16
0 0 0 0 0 0 0 0
Description
Section 15.5.3.3.9, "Maximum Receive Buffer Length
Access: Read/Write
Maximum Frame
0 1 1 0 0 0 0 0
Section 15.5.3.5.2, "MAC
(RxBD)."
(TBI)") is done through the
Freescale Semiconductor
31
0 0 0 0