Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 804

Enhanced Three-Speed Ethernet Controllers
15.5.3.6.14 Receive Pause Frame Packet Counter (RXPF)
Figure 15-65 describes the definition for the RXPF register.
Offset eTSEC1:0x2_46B4; eTSEC2:0x2_56B4
0
R
W
Reset
Figure 15-65. Receive Pause Frame Packet Counter Register Definition
Table 15-69 describes the fields of the RXPF register.
Bits Name
0–15 — Reserved
16–31 RXPF Receive PAUSE frame packet counter. Increments each time a PAUSE MAC control frame is
received with valid CRC and of lengths 64 to 1518 (non VLAN) or 1522 (VLAN).
15.5.3.6.15 Receive Unknown Opcode Packet Counter (RXUO)
Figure 15-66 describes the definition for the RXUO register.
Offset eTSEC1:0x2_46B8; eTSEC2:0x2_56B8
0
R
W
Reset
Figure 15-66. Receive Unknown OPCode Packet Counter Register Definition
Table 15-70 describes the fields of the RXUO register.
Bits Name
0–15 — Reserved
16–31 RXUO Receive unknown opcode counter. Increments each time a MAC control frame is received which contains
an opcode other than PAUSE, but the frame has valid CRC and length 64 to 1518 (non VLAN) or 1522
(VLAN).
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-86
—
All zeros
Table 15-69. RXPF Field Descriptions
—
All zeros
Table 15-70. RXUO Field Descriptions
15 16
Description
15 16
Description
Access: Read/Write
RXPF
Access: Read/Write
RXUO
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31