Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 806

Enhanced Three-Speed Ethernet Controllers
15.5.3.6.18 Receive Code Error Counter (RCDE)
Figure 15-69 describes the definition for the RCDE register.
Offset eTSEC1:0x2_46C4; eTSEC2:0x2_56C4
0
R
W
Reset
Table 15-73 describes the fields of the RCDE register.
Bits Name
0–15 — Reserved
16–31 RCDE Receive code error counter. Increments each time a valid carrier is present and at least one invalid data
symbol is detected.
15.5.3.6.19 Receive Carrier Sense Error Counter (RCSE)
Figure 15-70 describes the definition for the RCSE register.
Offset eTSEC1:0x2_46C8; eTSEC2:0x2_56C8
0
R
W
Reset
Figure 15-70. Receive Carrier Sense Error Counter Register Definition
Table 15-74 describes the fields of the RCSE register.
Bits Name
0–15 — Reserved
16–31 RCSE Receive false carrier counter. Counts the number of times that the carrier sense condition was lost or never
asserted when attempting to transmit a frame on a particular interface.
The count represented by an instance of this object is incremented at most once per transmission attempt,
even if the carrier sense condition fluctuates during a transmission attempt. The event is reported along with
the statistics generated on the next received frame, as defined by a 1 on TSEC n _RX_ER and an 0xE on
TSEC n _RXD. Only one false carrier condition can be detected and logged between frames.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-88
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Figure 15-69. Receive Code Error Counter Register Definition
Table 15-73. RCDE Field Descriptions
—
Table 15-74. RCSE Field Descriptions
15 16
All zeros
Description
15 16
All zeros
Description
Access: Read/Write
RCDE
Access: Read/Write
RCSE
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